# 2020(S08) Lecture:week 10

(Difference between revisions)
 Revision as of 11:24, 14 April 2008 (view source) (→Mapping these ideas to your project)← Previous diff Revision as of 11:34, 14 April 2008 (view source) (→Challenge 2: Reliable performance)Next diff → Line 31: Line 31: ==Challenge 2: Reliable performance== ==Challenge 2: Reliable performance== The first challenge today addressed catastrophic failure--if breaking a paperclip can be called “catastrophic.” The activity makes clear how engineers can enhance reliability by anticipating then obviating failure modes. Certainly, weaknesses can be tested and quantified, leading to reliability terms such as the "MTTF" ('''M'''ean '''T'''ime '''T'''o '''F'''ailure). And certainly there are simple things to try that lengthen “MTTF” such as specifying operating conditions (“don’t repeatedly bend the open clip back and forth") or including redundant functions (“use two paper clips when in doubt”). But catastrophic failure is only one way to fail. Today’s second challenge will consider another mode of failure, namely unreliable performance.
The first challenge today addressed catastrophic failure--if breaking a paperclip can be called “catastrophic.” The activity makes clear how engineers can enhance reliability by anticipating then obviating failure modes. Certainly, weaknesses can be tested and quantified, leading to reliability terms such as the "MTTF" ('''M'''ean '''T'''ime '''T'''o '''F'''ailure). And certainly there are simple things to try that lengthen “MTTF” such as specifying operating conditions (“don’t repeatedly bend the open clip back and forth") or including redundant functions (“use two paper clips when in doubt”). But catastrophic failure is only one way to fail. Today’s second challenge will consider another mode of failure, namely unreliable performance.
+ + ===Digital vs Analog Logic=== + As our starting point we’ll consider the simplest Boolean logic gate, the inverter or NOT gate. This gate has just one input. When that input has a logical value = 1 the output of the inverter is logical value = 0. And when the input value is = 0, the output is =1. The truth table and transfer curve for such a digital logic device is shown:
+ [[Image:NOTlogic.png|thumb|left|inverter logic, digital signal]] + [[Image:NOTtransfercurve.png|thumb|center|inverter transfer curve for digital signal]] + [[Image:StationaryBananas.png|thumb|right|expression profile for Eau d'coli]] + The inverter's transfer curve should remind you, just a little, of the shape of the curve we’ve already seen for the wintergreen and banana smell generator in the Eau d'coli project. Recall that the devices in this cell are controlled so that the wintergreen scent is generated only in log phase growth of the cell and the banana scent is generated only in stationary phase. In fact if you examine the system level diagram that the team specified you'll see an inverter device regulating the salicylic acid to methyl salycilate.
+
+ [[Image:Overall MIT2006 Fullsystem.jpg]] +
+ ==Challenge 3: Reliable sources== ==Challenge 3: Reliable sources==

## Revision as of 11:34, 14 April 2008

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# Week 10 Tuesday

Accidents waiting to happen

Not all engineers are pessimists but since good designs anticipate failure modes, many engineers must at least consider Murphy’s Law (what can go wrong will go wrong) as they flesh out the details of their designs. Like Daedalus’ wax wings flown too close to the sun, even designs that work well have limits and breaking points. If an engineered object is to work reliably, then the designers will have to carefully examine its multiple points of failure, including the three that today’s challenges address: extreme forces, performance variations, and human fallibility.

## Challenge 1: Reliable materials/use

modified from a lesson described in Henry Petroski’s book, To Engineer is Human

Boxes of paper clips don’t usually come with “ a money back guarantee” since nearly everyone in the world who uses paperclips finds them a reliable way to hold a few pieces of paper together. But bend the paperclip wide a few times and it’s likely to break. How many times will that be? We’ll do a quick experiment to find out. Each of you will bend a paperclip back and forth until it breaks and we’ll plot the data on a histogram.

Did all the paperclips break after the same number of bends? If so, why? If not, why not?
Reason 1:
Reason 2:

### Mapping these ideas to your project

This paperclip challenge spotlights two modes of system failure, namely

1. fatigue of the materials that comprise the device and
2. application of uncharacteristic forces.
As you've seen these affect each paperclip to differing degrees. When thinking about biotechnologies, what is akin to “material fatigue”? What situations might be considered uncharacteristic? How cell to cell differences can be taken into account is touched on in the next challenge but here let's apply material and use variations to the Eau d’coli project from the MIT 2006 iGEM team. Recall, these bacterial cells were designed to smell like bananas when they reach stationary phase.

1. In your groups imagine at least two ways that the genetic material in this system might "fatigue" and how you'd know.
2. Next define at least two environmental conditions that would derail the system and decide how likely these conditions are.

## Challenge 2: Reliable performance

The first challenge today addressed catastrophic failure--if breaking a paperclip can be called “catastrophic.” The activity makes clear how engineers can enhance reliability by anticipating then obviating failure modes. Certainly, weaknesses can be tested and quantified, leading to reliability terms such as the "MTTF" (Mean Time To Failure). And certainly there are simple things to try that lengthen “MTTF” such as specifying operating conditions (“don’t repeatedly bend the open clip back and forth") or including redundant functions (“use two paper clips when in doubt”). But catastrophic failure is only one way to fail. Today’s second challenge will consider another mode of failure, namely unreliable performance.

### Digital vs Analog Logic

As our starting point we’ll consider the simplest Boolean logic gate, the inverter or NOT gate. This gate has just one input. When that input has a logical value = 1 the output of the inverter is logical value = 0. And when the input value is = 0, the output is =1. The truth table and transfer curve for such a digital logic device is shown:

inverter logic, digital signal
inverter transfer curve for digital signal
expression profile for Eau d'coli

The inverter's transfer curve should remind you, just a little, of the shape of the curve we’ve already seen for the wintergreen and banana smell generator in the Eau d'coli project. Recall that the devices in this cell are controlled so that the wintergreen scent is generated only in log phase growth of the cell and the banana scent is generated only in stationary phase. In fact if you examine the system level diagram that the team specified you'll see an inverter device regulating the salicylic acid to methyl salycilate.

# Week 10 Thursday

==Challenge: Ownership and Sharing==